The present invention relates to a semiconductor device manufacturing method. Conventionally, as means for enhancing the performance of transistors, a stress memorization technique (SMT) is employed. A stress memorization technique is disclosed in, for example, Japanese Patent Laid-Open Nos. 2007-134718 and 2007-27747.
A stress memorization technique is intended to enhance the performance of transistors by applying stresses to the transistors, and known for, for example, enhancing the electron mobility of a transistor by applying a tensile stress to the transistor and enhancing the hole mobility of a transistor by applying a compressive stress to the transistor.
As a method for applying a stress to a transistor, a stress layer is formed on a transistor, and thermal treatment is performed so that a stress is memorized in the diffusion region or gate polysilicon of the transistor. Consequently, the electron mobility and the hole mobility of the channel region will be enhanced. After the thermal treatment, the stress layer is removed.
Here, the following method can be considered as a more specific manufacturing method in which a stress layer is formed to enhance the performance of transistors.
First, as shown in FIG. 11(A), a silicon oxide film 91 is formed over NMOS transistors 81 in a NMOS forming region, a PMOS transistor 82 in a PMOS forming region, and a gate structure 83.
Next, as shown in FIG. 11(B), a stress layer 92 is formed over the NMOS transistors 81 in the NMOS forming region, the PMOS transistor 82 in the PMOS forming region, and the gate structure 83.
Subsequently, as shown in FIG. 12(A), a photoresist 93 is formed over the NMOS transistors 81, and a portion of the stress layer 92 is removed over the PMOS transistor 82 and the gate structure 83.
In this case, the stress layer 92 is removed by dry etching.
Next, as shown in FIG. 12(B), after removal of the photoresist 93, the substrate is subjected to thermal treatment. Furthermore, as shown in FIG. 13(A), the stress layer 92 is removed by wet etching.
Subsequently, for example, a silicide film is formed in a necessary area by the following procedure. In order to form a silicide film in a region excluding the gate structure 83, as shown in FIG. 13(B), a silicide blocking film 94 is formed. Furthermore, as shown in FIG. 14, a photoresist 95 is formed only over the gate structure 83, and portions of the silicon oxide film 91 and the silicide blocking film 94 are removed over the NMOS transistors 81 and the PMOS transistor 82. No silicide film is formed over the region where the silicide blocking film 94 is left.
Subsequently, although not shown, a silicide film is formed over the diffusion regions of the NMOS transistors 81 and the PMOS transistor 82.
Here, the present inventors have noticed that the above-described semiconductor device manufacturing method has the following problems.
When the stress layer 92 is removed by dry etching, the silicon oxide film 91 underlying the stress layer 92 is removed, too (see FIG. 12(A)). Consequently, the portion of the silicon oxide film 91 over the PMOS transistor 82 becomes thinner compared to the portion of the silicon oxide film 91 over the NMOS transistors 81.
The portion of the silicon oxide film 91 over the PMOS transistor 82 becomes thin due to preliminary cleaning for the step of performing thermal treatment of the substrate (FIG. 12(B)) after the removal of the photoresist 93 and the step of removing the stress layer 92 by wet etching (FIG. 13). Furthermore, as shown in FIG. 14, when the surface of the substrate is exposed by removing a portion of the silicon oxide film 91, the substrate surface (diffusion layer) where the PMOS transistor 82 is formed will be excessively etched. This excessive etching removes impurities doped in the diffusion layer, which may result in an increase in parasitic resistance and/or a decrease in on-state current.